1. Field of the Invention
The present invention relates to a thin film transistor, an organic light emitting device (OLED) comprising the same, and a method for fabricating the OLED and, more particularly, to a series thin film transistor, an active matrix OLED comprising the same, and a method for fabricating the active matrix OLED.
2. Discussion of the Related Art
Typically, an OLED is an emissive display of a fluorescent organic compound that has been electrically excited to emit light. Depending upon how the display pixels are driven, OLEDs are classified as either passive or active matrix (AM) OLEDs. In an AM OLED, each pixel is driven by its own pixel driving circuit. The AM OLED uses less power than a passive matrix (PM) OLED, and the AM OLED can be implemented in a larger area and at a higher resolution. The pixel driving circuit includes a switching thin film transistor (TFT), a driving TFT, and a capacitor for its basic configuration. Additional TFTs may be added to the pixel driving circuit to compensate for the threshold voltage, carrier mobility, etc., of the TFTs. In this case, the driving TFTs may be connected to one another by means of a local interconnection line. Such serially interconnected TFTs are referred to as a series TFT.
FIG. 1 shows a cross-sectional view of an OLED having a series TFT in accordance with the prior art.
Referring to FIG. 1, a first patterned semiconductor layer 30 and a second patterned semiconductor layer 35 are positioned on substrate 10. The first patterned semiconductor layer 30 consists of a first channel region 30a and first source/drain regions 30b, 30c, which are formed at both sides of the first channel region 30a. The second patterned semiconductor layer 35 consists of a second channel region 35a and second source/drain regions 35b, 35c, which are formed at both sides of the second channel region 35a. A first gate electrode 50 and a second gate electrode 55 are positioned above the first channel region 30a and the second channel region 35a, respectively. A gate insulating layer 40 is interposed between the channel regions 30a, 35a and the gate electrodes 50, 55. An interlayer 60 is formed to cover the gate electrodes 50, 55, the gate insulating layer 40, and the semiconductor layers 30, 35. In interlayer 60 and gate insulating layer 40, a first contact hole 61 and a second contact hole 63 are formed to expose the first source/drain regions 30b, 30c, respectively, and a third contact hole 65 and a fourth contact hole 67 are formed to expose the second source/drain regions 35b, 35c, respectively. Also formed in the interlayer 60 and the gate insulating layer 40, are the first source/drain electrodes 71, 73 and the second source/drain electrodes 75, 77. Finally, an interconnection line 74 is formed on the interlayer 60. Consequently, the first source/drain electrodes 71, 73 are contacted with the first source/drain regions 30b, 30c, which are exposed in the first and second contact holes 61, 63; the second source/drain electrodes 75, 77 are contacted with the second source/drain regions 35b, 35c, which are exposed in the third and fourth contact holes 65, 67. and The interconnection line 74 serially connects the first source/drain electrode 73 to the second source/drain electrode 75. Thus, the first semiconductor layer 30 and the second semiconductor layer 35 are serially connected to each other by the first source/drain electrode 73, the second source/drain electrode 75, and the interposed interconnection line 74. As a result, the first TFT 51 and the second TFT 56 are serially connected to each other.
In order to implement this series TFT, two contact holes are required, namely the second contact hole 63 for forming the first source/drain electrode 73 and the third contact hole 65 for forming the second source/drain electrode 75. Because these two contact holes are required to be formed on the substrate, this increases the size of the area that the pixel driving circuit occupies, which adversely impacts the ability to increase the aperture ratio. In addition, having two contact holes adversely impacts a design rule that peripheral patterns should maintain regular intervals with respect to the contact holes.